DESCRIPTION

The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock.

FEATURES

■ Max. shift frequency of 600MHz

■ Max. Clock to Q delay of 1200ps

■ IEE min. of –150mA

■ Industry standard 100K ECL levels

■ Extended supply voltage option: VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved noise immunity

■ Internal 75KΩ input pull-down resistors

■ 70 faster than Fairchild 300K at lower power

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC packages