DESCRIPTION

The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter.

FEATURES

■ Max. shift frequency of 700MHz

■ Clock to Q delay max. of 1100ps

■ Sn to TC speed improved by 50

■ Sn set-up and hold time reduced by more than 50

■ IEE min. of –170mA

■ Industry standard 100K ECL levels

■ Internal 75KΩ input pull-down resistors

■ Extended supply voltage option: VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved noise immunity

■ 50 faster than Fairchild 300K at lower power

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC packages