Features

 1-T 80C51 Central Processing Unit

 MG82F6D17 with 16K Bytes flash ROM

━ ISP memory zone could be optioned as 0.5KB/1.0KB~7.5KB

━ Flexible IAP size by software configured

━ Code protection for flash memory access

━ Flash write/erase cycle: 20,000

━ Flash data retention: 100 years at 25°C

 Default MG82F6D17 Flash space mapping

 AP Flash default mapping (13.5KB, 0000h~35FFh)

 IAP Flash default mapping (1.0KB, 3600h~39FFh)

 ISP Flash default mapping (1.5KB, 3A00h~3FFFh), ISP Boot code

 Data RAM: 1K Bytes

━ On-chip 256 bytes scratch-pad RAM

━ 768 bytes expanded RAM (XRAM) for MG82F6D17

━ Support page select on XRAM access in MG82F6D17

 Dual data pointer

 Provide one channel DMA engine

━ P2P, M2P, P2M

━ Memory target: XRAM

━ Peripheral target: UART0, UART1, SPI, TWI0/I2C0, ADC12 & CRC16

━ Timer 5 and Timer 6 are used for DMA, but it also can be traded as independent timer when DMA not in use

 Interrupt controller

━ 16 sources, four-level-priority interrupt capability

━ Three external interrupt inputs, nINT0, nINT1 and nINT2 with glitch filter

━ All external interrupts support High/Low level or Rising/Falling edge trigger

 Total 9/11 timers in MG82F6D17

━ RTC Timer and WDT Timer

━ Timer 0, Timer 1, Timer 2 and Timer 3

━ PCA0, Program Counter Array 0

━ S0 BRG and S1 BRG

━ If Timer 2/3 in split mode, total 11 timers

 Four 16-bit timer/counters, Timer 0, Timer 1, Timer 2 and Timer 3

━ X12 mode and timer clock output function

━ Synchronous Run-Enable on all timer (same function on Stop and Reload)

━ New 5 operating modes in Timer 2/3 with 8 clock sources and 8 capture sources

━ Timer 2/3 can be split to two 8-bit timers

━ Clock Count Output (CCO) on T2CKO and T3CKO

━ All timers support PWM mode

 One Programmable 16-bit counter/timer Arrays (PCA0) with 8 Compare/PWM modules

━ PCA0 Features

 1-T 80C51 Central Processing Unit

 MG82F6D17 with 16K Bytes flash ROM

━ ISP memory zone could be optioned as 0.5KB/1.0KB~7.5KB

━ Flexible IAP size by software configured

━ Code protection for flash memory access

━ Flash write/erase cycle: 20,000

━ Flash data retention: 100 years at 25°C

 Default MG82F6D17 Flash space mapping

 AP Flash default mapping (13.5KB, 0000h~35FFh)

 IAP Flash default mapping (1.0KB, 3600h~39FFh)

 ISP Flash default mapping (1.5KB, 3A00h~3FFFh), ISP Boot code

 Data RAM: 1K Bytes

━ On-chip 256 bytes scratch-pad RAM

━ 768 bytes expanded RAM (XRAM) for MG82F6D17

━ Support page select on XRAM access in MG82F6D17

 Dual data pointer

 Provide one channel DMA engine

━ P2P, M2P, P2M

━ Memory target: XRAM

━ Peripheral target: UART0, UART1, SPI, TWI0/I2C0, ADC12 & CRC16

━ Timer 5 and Timer 6 are used for DMA, but it also can be traded as independent timer when DMA not in use

 Interrupt controller

━ 16 sources, four-level-priority interrupt capability

━ Three external interrupt inputs, nINT0, nINT1 and nINT2 with glitch filter

━ All external interrupts support High/Low level or Rising/Falling edge trigger

 Total 9/11 timers in MG82F6D17

━ RTC Timer and WDT Timer

━ Timer 0, Timer 1, Timer 2 and Timer 3

━ PCA0, Program Counter Array 0

━ S0 BRG and S1 BRG

━ If Timer 2/3 in split mode, total 11 timers

 Four 16-bit timer/counters, Timer 0, Timer 1, Timer 2 and Timer 3

━ X12 mode and timer clock output function

━ Synchronous Run-Enable on all timer (same function on Stop and Reload)

━ New 5 operating modes in Timer 2/3 with 8 clock sources and 8 capture sources

━ Timer 2/3 can be split to two 8-bit timers

━ Clock Count Output (CCO) on T2CKO and T3CKO

━ All timers support PWM mode

 One Programmable 16-bit counter/timer Arrays (PCA0) with 8 Compare/PWM modules

━ PCA0 has 6 CCP (Capture/Compare/PWM) modules and 2 CP (Compare/PWM) modules

━ Reloadable 16-bit base counter to support variable length PWM

━ Up to 144 MHz clock source from on-chip CKM

━ Capture mode, 16-bit software timer mode and High speed output mode

━ Buffered capture mode to monitor narrow pulse input

━ Variable 8/10/12/16-bit PWM mode, the PCA can be configured to:

 Up to 8 channels un-buffered 10/12/16-bit PWM, or6 CCP (Capture/Compare/PWM) modules and 2 CP (Compare/PWM) modules

━ Reloadable 16-bit base counter to support variable length PWM

━ Up to 144 MHz clock source from on-chip CKM

━ Capture mode, 16-bit software timer mode and High speed output mode

━ Buffered capture mode to monitor narrow pulse input

━ Variable 8/10/12/16-bit PWM mode, the PCA can be configured to:

 Up to 8 channels un-buffered 10/12/16-bit PWM, or