Key Features

• Support octaflash Interface with Simultaneous Read while Write operations

• Support DTR (Double Transfer Rate) Mode

• Support clock frequency up to 200MHz

2. GENERAL DESCRIPTION

MX25UW51245G is 512Mb bits Octal interface Serial NOR Flash memory, which is configured as 67,108,864 x 8 internally. MX25UW51245G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

The MX25UW51245G octaflash provides multiple bank architecture with Simultaneous Read while Write operations.

The sequential read operation can be occur in any of the three banks which is not been programmed or erased.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Meanwhile, the read operation can be executing in another bank .

Program command is executed on byte, word or page (256 bytes) basis. Erase command is executed on sector (4K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register and RWW status register are included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25UW51245G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.