GENERAL DESCRIPTION

The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.

The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis.

FEATURES

GENERAL

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• Serial Peripheral Interface compatible -- Mode 0 and Mode 3

• 33,554,432 x 1 bit structure or 16,777,216 x 2 bits (Dual Output mode) structure

• 1024 Equal Sectors with 4K byte each

- Any Sector can be erased individually

• 64 Equal Blocks with 64K byte each

- Any Block can be erased individually

• Program Capability

- Byte base

- Page base (256 bytes)

• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE

• High Performance

- Fast access time: 86MHz serial clock

- Serial clock of Dual Output mode : 80MHz

- Fast program time: 0.6ms(typ.) and 3ms(max.)/page

- Byte program time: 9us (typical)

- Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block

• Low Power Consumption

- Low active read current: 25mA(max.) at 86MHz

- Low active programming current: 15mA (typ.)

- Low active sector erase current: 9mA (typ.)

- Standby current: 15uA (max.)

- Deep power-down mode 2uA (typical)

• Typical 100,000 erase/program cycles

• 20 years of data retention