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MT90价格
参考价格：￥168.3193
型号：MT9041AP 品牌：Microsemi 备注：这里有MT90多少钱，2025年最近7天走势，今日出价，今日竞价，MT90批发/采购报价，MT90行情走势销售排行榜，MT90报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
5mm Dome Top Ultra Bright Emmiter Features High output power High luminous intensity Narrow beam angle High reliability | Marktech |   | ||
5mm Red Ultra Bright Emtter Peak Emission Wavelength: 660nm The MT900A-UR is a red T 1 3/4, 5mm water clear LED designed for applications requiring high brightness and high reliability in a wider angle package. FEATURES > High Luminous Intensity > High Reliability / High Power Output > Excellent Optical / Mechanical Axi | Marktech | | ||
5mm Dome Top Ultra Bright Emitter Peak Emission Wavelength: 660nm The MT900A-UR2 is a red T 1 3/4, 5mm water clear LED designed for applications requiring high power output and high reliability in a wider angle package. It can be custom sorted for specific power output ranges FEATURES > High Output Power > High Reliability > | Marktech | | ||
Multi-Rate Parallel Access Circuit Description The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability of handling up to 3072 c | Mitel | | ||
Multi-Rate Parallel Access Circuit Description The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability of handling up to 3072 c | Mitel | | ||
Octal IMA/UNI PHY Device Description The MT90220 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90220 architecture, up to 8 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, tradit | Mitel | | ||
Octal IMA/UNI PHY Device Description The MT90220 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90220 architecture, up to 8 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, tradit | Mitel | | ||
Quad IMA/UNI PHY Device Description The MT90221 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90221 architecture, up to 4 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, tradit | Mitel | | ||
Quad IMA/UNI PHY Device Description The MT90221 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90221 architecture, up to 4 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, tradit | Mitel | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 Synchronizer Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces | ZARLINK Zarlink Semiconductor Inc | | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by | ZARLINK Zarlink Semiconductor Inc | | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by | ZARLINK Zarlink Semiconductor Inc | | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 Synchronizer Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces | ZARLINK Zarlink Semiconductor Inc | | ||
Multiple Output Trunk PLL Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1. | Mitel | | ||
Multiple Output Trunk PLL Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1. | Mitel | | ||
T1/E1 System Synchronizer Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a | Mitel | | ||
T1/E1 System Synchronizer Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a | Mitel | | ||
Global Digital Trunk Synchronizer Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1. | Mitel | | ||
Global Digital Trunk Synchronizer Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1. | Mitel | | ||
Multitrunk System Synchronizer Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith | Mitel | | ||
Multitrunk System Synchronizer Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith | Mitel | | ||
T1/E1 System Synchronizer Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 System Synchronizer Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 System Synchronizer Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1/OC3 System Synchronizer Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu | Mitel | | ||
T1/E1/OC3 System Synchronizer Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu | Mitel | | ||
T1/E1/OC3 System Synchronizer Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu | Mitel | | ||
T1/E1/OC3 System Synchronizer Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1/OC3 System Synchronizer Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 System Synchronizer with Holdover Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect | ZARLINK Zarlink Semiconductor Inc | | ||
T1/E1 System Synchronizer with Holdover Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect | ZARLINK Zarlink Semiconductor Inc | | ||
Multi-Channel ATM AAL1 SAR Description The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly t | Mitel | | ||
Multi-Channel ATM AAL1 SAR Description The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly t | Mitel | | ||
High-Speed Isochronous Multiplexer Description The High-Speed Isochronous Multiplexer integrated circuit multiplexes up to eight Serial Telecom (ST-BUS) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete elect | Mitel | | ||
High-Speed Isochronous Multiplexer Description The High-Speed Isochronous Multiplexer integrated circuit multiplexes up to eight Serial Telecom (ST-BUS) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete elect | Mitel | | ||
Octal T1/E1/J1 Framer Description The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T. An extensive | ZARLINK Zarlink Semiconductor Inc | | ||
Octal T1/E1/J1 Framer Description The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T. An extensive | ZARLINK Zarlink Semiconductor Inc | | ||
Octal T1/E1/J1 Framer Description The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T. An extensive | ZARLINK Zarlink Semiconductor Inc | | ||
CMOS E2/E3 Framer (E2/E3F) Description The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to one of four CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line circuitry with either dual rail or NRZ signals. On the termin | Mitel | | ||
CMOS E2/E3 Framer (E2/E3F) Description The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to one of four CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line circuitry with either dual rail or NRZ signals. On the termin | Mitel | | ||
CMOS DS3 Framer (DS3F) Description The MT90733 DS3 Framer (DS3F) is designed for mapping broadband payloads into the DS3 frame format, which meets ANSI’s T1.107-1988 and supplement T1.107a-1990. Features • DS3 payload access in either bit-serial or nibble-parallel mode • C-bit parity or M13 operating mode • Separat | Mitel | | ||
CMOS DS3 Framer (DS3F) Description The MT90733 DS3 Framer (DS3F) is designed for mapping broadband payloads into the DS3 frame format, which meets ANSI’s T1.107-1988 and supplement T1.107a-1990. Features • DS3 payload access in either bit-serial or nibble-parallel mode • C-bit parity or M13 operating mode • Separat | Mitel | | ||
T1/E1/J1 Single Chip Transceiver Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 (T1 mode) or PCM 30 (E1 mode) framer with a Line Interface Unit (LIU). Features • Combined E1 (PCM 30) and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with o | Mitel | | ||
T1/E1/J1 Single Chip Transceiver Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 (T1 mode) or PCM 30 (E1 mode) framer with a Line Interface Unit (LIU). Features • Combined E1 (PCM 30) and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with o | Mitel | | ||
T1/E1/J1 Single Chip Transceiver Description The MT9074 is a single chip device, operable in either T1 or E1 mode, integrating either an advanced T1 (T1 mode) or PCM 30 (E1 mode) framer with a Line Interface Unit (LIU). Features • Combined E1 (PCM 30) and T1 (D4/ESF) framer, Line Interface Unit (LIU) and link controller with o | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for S a bits and channel 16. The LIU interf | ZARLINK Zarlink Semiconductor Inc | | ||
E1 Single Chip Transceiver Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU inte | Mitel | | ||
E1 Single Chip Transceiver Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for S a bits and channel 16. The LIU interf | ZARLINK Zarlink Semiconductor Inc | |
MT90产品属性
- 类型
描述
- 型号
MT90
- 制造商
TE CONNECTIVITY P&B
- 功能描述
MT900622(MT3330C4)
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ZARLINK |
24+ |
NA/ |
49 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
ZARLINK |
2016+ |
BGA |
6000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
ZARLNK |
20+ |
BGA |
35830 |
原装优势主营型号-可开原型号增税票 |
|||
ZARLINK |
07+ |
BGA |
80 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
MITEL |
23+ |
BGA |
198589 |
原厂原装正品现货!! |
|||
MEDIATEK |
23+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
|||
ZARLINK |
23+ |
BGA |
9800 |
全新原装现货,假一赔十 |
|||
ZARLINK |
25+23+ |
BGA |
22156 |
绝对原装正品全新进口深圳现货 |
|||
ZARLINK |
22+ |
BGA |
3000 |
原装正品,支持实单 |
|||
MITEL |
25+ |
BGA |
4500 |
全新原装、诚信经营、公司现货销售! |
MT90规格书下载地址
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