CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmi

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

Advanced T1/CEPT Digital Trunk PLL

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmi

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmi

Advanced T1/CEPT Digital Trunk PLL

Description\nThe MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmis • Provides T1 clock at 1.544 MHz locked to an 8kHz reference clock (frame pulse)\n• Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock\n• Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak\n•Typical jitter atten;

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

CMOS ST-BUS??FAMILY Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

Advanced T1/CEPT Digital Trunk PLL

Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT tran

ADJUSTABLE LOW DROPOUT REGULATOR

DESCRIPTION The Microsemi LX8941 is an adjustable, low dropout regulator rated for more than 1A of output current. It can regulate with as low as 0.8V headroom between the input and output voltages, at 1A output current, thus minimizing power dissipation. In addition, it can be used in applicatio

1.5 W mono Bridge Tied Load BTL audio amplifier

文件：370.14 Kbytes Page：21 Pages

1.5 W mono Bridge Tied Load BTL audio amplifier

文件：370.14 Kbytes Page：21 Pages