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型号	功能描述	生产厂家企业	LOGO
MT5C1009	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE	AUSTIN	AUSTIN
MT5C1009	All inputs and outputs are TTL compatible 文件：199.58 Kbytes Page：17 Pages	MICROSS	MICROSS
MT5C1009C-15/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-15SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-20/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-20SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-25/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-25SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-35/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-35SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-45/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-45SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-55/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-55SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-70/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009C-70SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-15/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-15SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-20/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-20SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-25/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-25SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-35/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-35SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-45/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-45SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-55/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-55SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-70/XT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009CW-70SLASHXT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-15/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-15SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-20/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-20SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-25/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-25SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-35/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-35SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-45/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-45SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-55/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-55SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-70/883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009DCJ-70SLASH883C	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-15L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-15LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-20L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-20LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-25L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-25LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-35L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-35LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-45L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-45LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-55L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-55LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-70L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009E-70LSLASHIT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN
MT5C1009EC-15L/IT	128K x 8 SRAM WITH CHIP & OUTPUT ENABLE GENERAL DESCRIPTION The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. For design flexibility in high-	AUSTIN	AUSTIN

MT5C1009产品属性

类型
描述
型号
MT5C1009
制造商
AUSTIN
制造商全称
Austin Semiconductor
功能描述
128K x 8 SRAM WITH CHIP & OUTPUT ENABLE

MT5C1009供应商更多...

更新时间：2025-11-20 17:43:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市赛特兴科技有限公司	MT5C1009CW-45	ASI	QQ咨询	CDIP	135	全新原装研究所指定供货商	询价
贸泽芯城（深圳）电子科技有限公司	MT5C1009	ASI	23+	128K8	14960	原厂授权一级代理,专业海外优势订货,价格优势、品种	询价
深圳市振宏微科技有限公司	MT5C1009EC-25	MT	23+	NA	146	专做原装正品,假一罚百!	询价
深圳市美思瑞电子科技有限公司	MT5C1009C-35/883C	ASI	22+	cdip	12245	现货,原厂原装假一罚十!	询价
标准国际(香港)有限公司	MT5C1009C-45L/883C	MT5C1009C-45L/883C	25+	51	51		询价
深圳市东来宝电子科技有限公司	MT5C1009CW-35	ASI	24+	CDIP	22055	郑重承诺只做原装进口现货	询价
深圳市河锋鑫科技有限公司	MT5C1009CW-70	ASI	2021+		60000	原装现货，欢迎询价	询价
深圳市得捷芯城科技有限公司	MT5C1009EC-35L	ASI	24+	NA/	543	优势代理渠道,原装正品,可全系列订货开增值税票	询价
海芯未来半导体电子（深圳）有限公司	MT5C1009EC-25/883C	ASI	25+	CLCC32	27	只做原装进口!正品支持实单!	询价
深圳市毅创弘电子科技有限公司	MT5C1009C-25L	N/A	24+	NA	66800	原厂授权一级代理,专注汽车、医疗、工业、新能源！	询价

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MT5C1009产品属性

MT5C1009供应商更多...

MT5C1009芯片相关品牌

MT5C1009规格书下载地址

MT5C1009参数引脚图相关

MT5C1009数据表相关新闻

MT61K512M32KPA-21:U

MT61K512M32KPA-24:U

MT53E512M32D1ZW-046 IT:B TR 动态随机存取存储器

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