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型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
---|---|---|---|---|
MT5C1008 | 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | ||
MT5C1008 | 128K x 8 SRAM WITH DUAL CHIP ENABLE | AUSTIN | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN |
MT5C1008产品属性
- 类型
描述
- 型号
MT5C1008
- 制造商
AUSTIN
- 制造商全称
Austin Semiconductor
- 功能描述
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS
IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
ASI |
24+ |
NA/ |
34 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
MT |
25+ |
CDIP |
996880 |
只做原装,欢迎来电资询 |
|||
N/A |
24+ |
NA |
990000 |
明嘉莱只做原装正品现货 |
|||
24+ |
SOJ32 |
35210 |
一级代理/放心采购 |
||||
MT |
24+ |
CDIP |
13500 |
免费送样原盒原包现货一手渠道联系 |
|||
Micross/ASI |
25+23+ |
BGA |
19520 |
绝对原装正品全新进口深圳现货 |
|||
ASI |
25+ |
DIP |
4500 |
全新原装、诚信经营、公司现货销售! |
|||
ASI |
23+ |
CDIP |
3200 |
绝对全新原装!优势供货渠道!特价!请放心订购! |
|||
ASI |
QQ咨询 |
DIP |
1453 |
全新原装 研究所指定供货商 |
|||
Micron |
8 |
公司优势库存 热卖中!! |
MT5C1008芯片相关品牌
MT5C1008规格书下载地址
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- MT5C1005EC-20L/883C
- MT5C1005EC-20/XT
- MT5C1005EC-20/IT
- MT5C1005EC-20/883C
- MT5C1005C-20/IT
- MT5C1005C-20/883C
- MT5C1005C-15L/XT
- MT5C1005C-15L/IT
- MT5C1005C-15L/883C
- MT5C1005C-15/XT
- MT5C1005C-15/IT
- MT5C1005C-15/883C
- MT5C1005_05
- MT5C1005
- MT5B5
- MT5A5
- MT5815
- MT5750
- MT5715
- MT550-Y
- MT550-O
- MT550-G
- MT5460G
- MT5330
- MT52K3
- MT52K1
- MT51XX
- MT516
- MT5140
- MT5139
- MT511
- MT5103
- MT5102
- MT5101
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2020-11-21
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