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MT5C1008

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

MT5C1008

128K x 8 SRAM WITH DUAL CHIP ENABLE

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION\nThe MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology.FEATURES\n• High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns\n• Battery Backup: 2V data retention\n• • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns\n• Battery Backup: 2V data retention\n• Low power standby\n• High-performance, low-power CMOS process\n• Single +5V (+10%) Power Supply\n• Easy memory expansion with CE1, CE2, and OE options.\n• All inputs and outputs are TTL compatible;

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio

AUSTIN

MT5C1008产品属性

  • 类型

    描述

  • 型号

    MT5C1008

  • 制造商

    AUSTIN

  • 制造商全称

    Austin Semiconductor

  • 功能描述

    128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

更新时间:2026-5-14 19:34:00
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32
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1500
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