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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
MT5C1008 | 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN |   | |
MT5C1008 | 128K x 8 SRAM WITH DUAL CHIP ENABLE | AUSTIN | | |
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE ULTRA LOW POWER GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | | ||
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. FEATURES • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns • Battery Backup: 2V data retentio | AUSTIN | |
MT5C1008产品属性
- 类型
描述
- 型号
MT5C1008
- 制造商
AUSTIN
- 制造商全称
Austin Semiconductor
- 功能描述
128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
MICRON/美光 |
2402+ |
DIP32 |
8324 |
原装正品!实单价优! |
|||
MT |
23+ |
CLCC32 |
18 |
全新原装正品现货,支持订货 |
|||
ASI |
24+ |
DLCC32 |
5000 |
全新原装正品,现货销售 |
|||
MICRON |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
ASI |
23+ |
SOP32 |
37 |
长期有货,欢迎来电咨询。 |
|||
MICRON |
23+ |
SOJ |
12800 |
公司只有原装 欢迎来电咨询。 |
|||
MICROSS |
24+ |
DIP |
18000 |
原装正品 有挂有货 假一赔十 |
|||
ASI |
24+ |
DLCC32 |
25836 |
新到现货，只做全新原装正品 |
|||
MICRONT |
24+ |
QFP |
37500 |
原装正品现货,价格有优势! |
|||
ASI |
22+ |
AUDIP |
12245 |
现货,原厂原装假一罚十! |
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MT5C1008规格书下载地址
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- MT5C1005EC-20/XT
- MT5C1005EC-20/IT
- MT5C1005EC-20/883C
- MT5C1005C-20/IT
- MT5C1005C-20/883C
- MT5C1005C-15L/XT
- MT5C1005C-15L/IT
- MT5C1005C-15L/883C
- MT5C1005C-15/XT
- MT5C1005C-15/IT
- MT5C1005C-15/883C
- MT5C1005_05
- MT5C1005
- MT5B5
- MT5A5
- MT5815
- MT5750
- MT5715
- MT550-Y
- MT550-O
- MT550-G
- MT5460G
- MT5330
- MT52K3
- MT52K1
- MT51XX
- MT516
- MT5140
- MT5139
- MT511
- MT5103
- MT5102
- MT5101
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2020-11-21
DdatasheetPDF页码索引
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