SYNCHRONOUS DRAM

Features • PC100-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full

128Mb: x32 SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

文件：3.55494 Mbytes Page：79 Pages

SDR SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

Features • PC100-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full

128Mb: x32 SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

文件：3.55494 Mbytes Page：79 Pages

128Mb: x32 SDRAM MT48LC4M32B2 ??1 Meg x 32 x 4 Banks

文件：3.55494 Mbytes Page：79 Pages