256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured

256KB and 512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms

RECTIFIER DIODE

RECTIFIER DIODE Repetitive voltage up to 2600 V Mean forward current 3180 A Surge current 33.6 kA

Quad GTL/GTL to LVTTL/TTL bidirectional latched translator

DESCRIPTION The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from th

Quad GTL/GTL to LVTTL/TTL bidirectional latched translator

DESCRIPTION The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from th

900 MHz DRIVER & RAMP SILICON MONOLITHIC INTEGRATED CIRCUIT

The MRFIC2004 is an integrated Driver and Ramp designed for transmitters operating in the 800 MHz to 1.0 GHz frequency range. The Ramp is an integrator which can be used for burst control for TDD/TDMA systems. The Driver uses a cascode configuration for high gain and reverse isolation. A power dow