250mA 低压差线性稳压器

MP8902是一款低噪声、低压差线性稳压器。它可以在2.7V至6.5V输入电压范围内工作，并提供2.5V、2.85V、3.3V输出电压，或在1.25V至5V范围内以2％的精度调节输出电压。\n\nMP8902可以提供高达250mA的负载电流。同时具有热过载保护功能。MP8902采用8引脚2mm × 2mm QFN 封装。 • 250mA 电流条件下提供250mV 低压差\n• 输出电压精度为2％\n• 可选固定输出电压：2.5V、2.85V或3.3V\n• 采用外部电阻分压器在1.25V至5V范围内调节输出电压\n• 输入电压可高达6.5V\n• 高PSRR\n• ----70dB @1kHz\n• ----30dB @1MHz\n• 负载调整率优于0.001％/ mA\n• 采用 低ESR 输出电容可稳定工作\n• 125μA 低接地电流\n• 内部热保护;

Low Dropout 250mA Linear Regulator

文件：573.16 Kbytes Page：9 Pages

Low Dropout 250mA Linear Regulator

文件：573.16 Kbytes Page：9 Pages

Low Dropout 250mA Linear Regulator

文件：573.16 Kbytes Page：9 Pages

DC FAN Motor Controller

Description The FAN8902 is a monolithic integrated circuit, designed for the PWM control of a DC fan motor current in an automotive systems. It allows the fan motor speed to be controlled linearly and efficiently. Features • Built-in PWM Current Control Circuit • Built-in 5V Regulator • Low S

3-Channel Clock Driver

Overview • The LB8902M is designed to drive a capacitive load at a high speed. • Suited for horizontal clock drive of CCD image sensor. Functions and Features • 3-channel inverter buffer amplifier. • Fast propagation time (10ns typ. for 100pF load). • Low-voltage operation available (5V min)

3-Channel Clock Driver

Overview • The LB8902M is designed to drive a capacitive load at a high speed. • Suited for horizontal clock drive of CCD image sensor. Functions and Features • 3-channel inverter buffer amplifier. • Fast propagation time (10ns typ. for 100pF load). • Low-voltage operation available (5V min)

Digital Audio Interface Receiver

Overview The LC8902 and LC8902Q are receiver LSIs for applications in which data is transmitted between digital audio equipment in the EIAJ format. These LSIs synchronize with the input signal and demodulate that signal to a regular format signal. Features • Built-in PLL circuit synchroniz

Digital Audio Interface Receiver

Overview The LC8902 and LC8902Q are receiver LSIs for applications in which data is transmitted between digital audio equipment in the EIAJ format. These LSIs synchronize with the input signal and demodulate that signal to a regular format signal. Features • Built-in PLL circuit synchroniz