Inverting Octal TRI-STATE Transceiver

文件：145.22 Kbytes Page：6 Pages

Inverting Octal TRI-STATE Transceiver

文件：145.22 Kbytes Page：6 Pages

Inverting Octal TRI-STATE Transceiver

文件：145.22 Kbytes Page：6 Pages

Octal bus transceiver; 3-state; true/inverting

GENERAL DESCRIPTION The 74HC/HCT643 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Octal bidirectional bus interface • True and inverting 3-state outputs • Output capabilit

Octal Bus Transceivers (with 3-state outputs)

Description Each device has an active enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HC640 transfers inverted data from one bus to other and the HD74HC643 transfe

Octal Bus Transceivers (with 3-state outputs)

Description Each device has an active enable G and a direction control input, DIR. when DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HC640 transfers inverted data from one bus to other and the HD74HC643 transfe

Octal Bus Transceivers (with 3-state outputs)

Description Each device has an active enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HC640 transfers inverted data from one bus to other and the HD74HC643 transfe

OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS INVERTING/NON INVERTING

DESCRIPTION The M54/74HC245, HC640 and HC643 utilise silicon gate C2MOS technology to achive operating speeds equivalent to LSTTL devices. Along with the low power dissipation and high noise immunity of standards C2MOS integrated circuit, it possesses the capability to drive 15 LSTTL loads. The