4-to-16 Line Decoder with Latch

General Description The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Sch

4-to-16 Line Decoder with Latch

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封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X4:16 24SOP 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X4:16 24SOP 集成电路（IC） 信号开关，多路复用器，解码器

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de