LOW-VOLTAGE CMOS

The MC74LVX74 is an advanced high speed CMOS D–type flip–flop. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: fmax = 145MHz (Typ) at VCC = 3.3V • Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C • Power Down Protection Provided o

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

LOW-VOLTAGE CMOS

The MC74LVX74 is an advanced high speed CMOS D–type flip–flop. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: fmax = 145MHz (Typ) at VCC = 3.3V • Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C • Power Down Protection Provided o

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

Dual D?뭈ype Flip?묯lop with Set and Clear

The MC74LVX74 is an advanced high speed CMOS D−type flip−flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V • Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C • Power Down

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

Dual D-Type Flip-Flop with Set and Clear

文件：113.9 Kbytes Page：7 Pages

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP 集成电路（IC） 触发器

Dual D-Type Flip-Flop with Set and Clear

文件：113.9 Kbytes Page：7 Pages

Dual D-Type Flip-Flop with Set and Clear

文件：113.9 Kbytes Page：7 Pages

LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS)

DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. ■ HIGH SPEED: fMAX = 145MHz

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

文件：93.74 Kbytes Page：7 Pages

Low Voltage Dual D-Type Positive Edge-Triggerednull Flip-Flop

文件：235.54 Kbytes Page：9 Pages