Dual 4-Stage Binary Ripple Counter with 첨2 and 첨5 Sections

Dual 4−Stage Binary Ripple Counter with ÷2 and ÷5 Sections High−Performance Silicon−Gate CMOS The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive

Dual 4-Stage Binary Ripple Counter with 첨2 and 첨5 Sections

Dual 4−Stage Binary Ripple Counter with ÷2 and ÷5 Sections High−Performance Silicon−Gate CMOS The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive

Dual 4?뭆tage Binary Ripple Counter with /2and /5 Sections High?뭁erformance Silicon?묰ate CMOS

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封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC COUNTER RPPL DUAL 4ST 16TSSOP 集成电路（IC） 计数器，除法器

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC COUNTER RPPL DUAL 4ST 16TSSOP 集成电路（IC） 计数器，除法器

Dual 4?뭆tage Binary Ripple Counter with /2and /5 Sections High?뭁erformance Silicon?묰ate CMOS

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Dual 4-Stage Binary Ripple Counter

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Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

DUAL DECADE RIPPLE COUNTER

DUAL DECADE RIPPLE COUNTER

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

High?밣erformance Silicon?밎ate CMOS

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