12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

12-BIT PARITY TREE

The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be consi

USB 2.0 Hi-Speed and Audio Switches with Negative Signal Capability and 짹15kV ESD

General Description The MAX14531E–MAX14534E high ESD-protected DP3T switches multiplex Hi-Speed (480 Mbps) USB signals, low/full-speed USB signals, and analog signals such as AC-coupled audio or video through any of three channels. These devices combine the low oncapacitance (CON) and low on-resi

12-bit Parity Tree

文件：65.31 Kbytes Page：4 Pages

12-bit Parity Tree

文件：65.31 Kbytes Page：4 Pages

13-input parity checker/generator

13-input parity checker/generator

13-input parity checker/generator

12-BIT PARITY TREE