Dual 64-Bit Static Shift Register

Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, re

Dual 64?묪it Static Shift Register

文件：90.67 Kbytes Page：6 Pages

Dual 64-Bit Static Shift Register

Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, re

Dual 64?묪it Static Shift Register

文件：90.67 Kbytes Page：6 Pages

Dual 64-Bit Static Shift Register

文件：109.55 Kbytes Page：5 Pages

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：串行至并行 包装：管件 描述：IC SHIFT REG DUAL 64BIT 16-SOIC 集成电路（IC） 移位寄存器

Dual 64?묪it Static Shift Register

文件：90.67 Kbytes Page：6 Pages

Dual 64?묪it Static Shift Register

文件：90.67 Kbytes Page：6 Pages

Dual 64-Bit Static Shift Register

文件：109.55 Kbytes Page：5 Pages

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：串行至并行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SHIFT REG DUAL 64BIT 16-SOIC 集成电路（IC） 移位寄存器

LOW-VOLTAGE CMOS OCTAL BUFFER

Low-Voltage Quiet CMOS Octal Buffer (3-State, Non-Inverting) The MC74LVQ244 is a high performance, non–inverting octal buffer operating from a 2.7 to 3.6V supply. The MC74LVQ244 is suitable for memory address driving and all TTL level bus oriented transceiver applications. • Designed for 2.7 to

Dual 64-Bit Static Shift Register

Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, re

Dual 64-Bit Static Shift Register

Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, re

Dual 64-bit Static Shift Register

Dual 64-bit Static Shift Register