Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

Quad Type D Flip?묯lop

文件：123.91 Kbytes Page：6 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 4BIT 16SOIC 集成电路（IC） 触发器

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

Quad Type D Flip?묯lop

文件：123.91 Kbytes Page：6 Pages

Quad Type D Flip-Flop

文件：149.44 Kbytes Page：6 Pages

Quad Type D Flip-Flop

文件：128.169 Kbytes Page：6 Pages

Quad Type D Flip?묯lop

文件：123.91 Kbytes Page：6 Pages

Quad Type D Flip?묯lop

文件：123.91 Kbytes Page：6 Pages

Quad Type D Flip-Flop

文件：149.44 Kbytes Page：6 Pages

Quad Type D Flip-Flop

文件：128.169 Kbytes Page：6 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 4BIT 16SOIC 集成电路（IC） 触发器

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

Quad Type D Flip-Flop

Quad Type D Flip-Flop The MC14175B quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously

Quadruple D-type Flip Flop

FEATURES ● Supply Voltage Range = 3 to 18V ● Output Compatible with One Low-power Schottky TTL Load ● Functional Equivalent to TTL74175