8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou

封装/外壳：16-DIP（0.300"，7.62mm） 功能：串行至并行 包装：管件 描述：IC SHIFT REGISTER 8STAGE 16-DIP 集成电路（IC） 移位寄存器

8?뭆tage Shift/Store Register with Three?뭆tate Outputs

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8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou

8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou

8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou

8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou

8-Stage Shift/Store Register with Three-State Outputs

The MC14094B combines an 8−stage shift register with a data latch for each stage and a 3−state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is for use in high−speed cascaded systems. The QSou