6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

5.0 V ECL 6-Bit 2:1 Mux-Register

The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchr • 1000MHz Min. Operating Frequency\n• 800ps Max. Clock to Output\n• Single-Ended Outputs\n• Asynchronous Master Resets\n• DualClocks\n• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\n• Internal Input Pulldown Resist;

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

5V ECL 6?륛it 2:1 MUX?륱egiste

文件：156.39 Kbytes Page：8 Pages

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

5V ECL 6?륛it 2:1 MUX?륱egiste

文件：156.39 Kbytes Page：8 Pages

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC MULTIPLEXER 6 X 2:1 28PLCC 集成电路（IC） 信号开关，多路复用器，解码器

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC MULTIPLEXER 6 X 2:1 28PLCC 集成电路（IC） 信号开关，多路复用器，解码器

5V ECL 6-Bit 2:1 MUX-Register

文件：128.699 Kbytes Page：8 Pages

5V ECL 6?륛it 2:1 MUX?륱egiste

文件：156.39 Kbytes Page：8 Pages

6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en