1:5 Clock Distribution Chip

Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and

3.3V ECL 1:5 Clock Distribution Chip

文件：127.8 Kbytes Page：6 Pages

3.3 V ECL 1:5 Clock Distribution Chip

文件：158.31 Kbytes Page：7 Pages

1:5 Clock Distribution Chip

Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and

3.3V ECL 1:5 Clock Distribution Chip

文件：127.8 Kbytes Page：6 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：托盘 描述：IC CLK BUFFER 2:5 1GHZ 20SOIC 集成电路（IC） 时钟缓冲器，驱动器

3.3 V ECL 1:5 Clock Distribution Chip

文件：158.31 Kbytes Page：7 Pages

3.3V ECL 1:5 Clock Distribution Chip

文件：127.8 Kbytes Page：6 Pages

3.3V ECL 1:5 Clock Distribution Chip

文件：127.8 Kbytes Page：6 Pages

3.3 V ECL 1:5 Clock Distribution Chip

文件：158.31 Kbytes Page：7 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 2:5 1GHZ 20SOIC 集成电路（IC） 时钟缓冲器，驱动器

3.3V ECL 1:5 Clock Distribution Chip

文件：127.8 Kbytes Page：6 Pages