첨4 Divider

Description The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

5.0 V ECL ÷·4 分频器

The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.015F capacitor. Also note that the VBB is designed to be used as an input • 650ps Propagation Delay\n• 4.0GHz Toggle Frequency\n• ESD Protection: > 1 KV HBM, > 100 V MM\n• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V\n• Internal Input Pulldown Resistors on CLK(s) and R.\n• Meets or Exceeds J;

5V ECL 첨4 Divider

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5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes Page：20 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

Divider

文件：171.39 Kbytes Page：8 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

Divider

文件：171.39 Kbytes Page：8 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DIVIDER X4 ECL DIFF 8-SOIC 集成电路（IC） 计数器，除法器

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：管件 描述：IC DIVIDER DIV X4 ECL DFF 8TSSOP 集成电路（IC） 计数器，除法器

Divider

文件：171.39 Kbytes Page：8 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：152.34 Kbytes Page：10 Pages

5V ECL 첨4 Divider

文件：155.56 Kbytes Page：10 Pages

5V/3.3V 첨 4 DIVIDER

DESCRIPTION The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be u

5V/3.3V 첨 4 DIVIDER

DESCRIPTION The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be u

5V/3.3V 첨 4 DIVIDER

DESCRIPTION The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be u

5V/3.3V 첨 4 DIVIDER

DESCRIPTION The SY10/100EL33/L are integrated ÷4 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be u