첨2 Divider

Description The MC10EL/100EL32 is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

5.0 V ECL ÷·2 分频器

The MC10EL/100EL32 is an integrateddivide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 F capacitor. Also note that the VBB is designed to be used as a • 510ps Propagation Delay\n• 3.0GHz Toggle Frequency\n• ESD Protection: > 1 KV HBM, > 100 V MM\n• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V\n• Internal Input Pulldown Resistors on CLK(s) and R.\n• Meets or Exceeds J;

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes Page：20 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

Divider

文件：171.35 Kbytes Page：8 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DIVIDER DIV X2 5V ECL 8-SOIC 集成电路（IC） 计数器，除法器

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

Divider

文件：171.35 Kbytes Page：8 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：管件 描述：IC DIVIDER DIV X2 ECL 5V 8TSSOP 集成电路（IC） 计数器，除法器

Divider

文件：171.35 Kbytes Page：8 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：155 Kbytes Page：9 Pages

5V ECL 첨2 Divider

文件：152.01 Kbytes Page：9 Pages

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

5V/3.3V 첨 2 DIVIDER

DESCRIPTION The SY10/100EL32V are integrated ÷2 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used

5V/3.3V 첨 2 DIVIDER

DESCRIPTION The SY10/100EL32V are integrated ÷2 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used