5V ECL Programmable Delay Chip

文件：158.37 Kbytes Page：12 Pages

封装/外壳：28-LCC（J 形引线） 功能：可编程 包装：卷带（TR） 描述：IC DELAY LINE 128TAP PROG 28PLCC 集成电路（IC） 延迟线

PROGRAMMABLE DELAY CHIP

Description The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elem

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications FEATURES ■ Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ≈20ps digital step resolution ■ Linear input for tighter res

PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT

文件：82.28 Kbytes Page：10 Pages