High-Linearity 1700MHz to 2200MHz Down- Conversion Mixer with LO Buffer/Switch

General Description The MAX9993 high-linearity down-conversion mixer provides 8.5dB of gain, +23.5dBm IIP3, and 9.5dB NF for UMTS, DCS, and PCS base-station applications. Features ♦ +23.5dBm Input IIP3 ♦ 1700MHz to 2200MHz RF Frequency Range ♦ 40MHz to 350MHz IF Frequency Range ♦ 1400MHz to

高线性度、1700MHz至2200MHz下变频混频器，带有LO缓冲器/开关

MAX9993高线性度下变频混频器能够为UMTS、DCS和PCS基站系统提供8.5dB增益、+23.55dBm IIP3和9.5dB的噪声系数。\n\n MAX9993在RF和LO端口集成了非平衡变压器、一个双输入LO可选开关、一个LO缓冲器、一个双平衡混频器和一个差分IF输出放大器。MAX9993需要典型值为+3dBm的LO驱动，确保电源电流低于230mA。\n\n MAX9993提供紧凑的20引脚、焊盘裸露的QFN封装(5mm x 5mm)。电特性保证在-40°C至+85°C温度范围内有效。\n\n 可提供MAX9993评估板；更多信息请与工厂联系。\n\n • +23.5dBm输入IIP3\n• RF频率范围为1700MHz至2200MHz \n• IF频率范围为40MHz至350MHz \n• LO频率范围为1400MHz至2000MHz \n• 转换增益为8.5dB \n• 噪声系数为9.5dB\n• 集成的LO缓冲器 \n• 开关可选(SPDT)，双LO输入 \n• 0至+6dBm的低LO驱动 \n• LO1至LO2隔离度为40dB;

1400MHz to 2000MHz LO Frequency

文件：251.53 Kbytes Page：7 Pages

High-Linearity 1700MHz to 2200MHz Down- Conversion Mixer with LO Buffer/Switch

General Description The MAX9993 high-linearity down-conversion mixer provides 8.5dB of gain, +23.5dBm IIP3, and 9.5dB NF for UMTS, DCS, and PCS base-station applications. Features ♦ +23.5dBm Input IIP3 ♦ 1700MHz to 2200MHz RF Frequency Range ♦ 40MHz to 350MHz IF Frequency Range ♦ 1400MHz to

封装/外壳：20-WQFN 裸露焊盘 包装：带 描述：IC MIXER 1.7-2.2GHZ DWN 20TQFN RF/IF，射频/中频和 RFID 射频混频器

封装/外壳：20-WQFN 裸露焊盘 包装：卷带（TR）带 描述：IC MIXER 1.7-2.2GHZ DWN 20TQFN RF/IF，射频/中频和 RFID 射频混频器

1400MHz to 2000MHz LO Frequency

文件：251.53 Kbytes Page：7 Pages

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg