High-Linearity 1700MHz to 2200MHz Down- Conversion Mixer with LO Buffer/Switch

General Description The MAX9993 high-linearity down-conversion mixer provides 8.5dB of gain, +23.5dBm IIP3, and 9.5dB NF for UMTS, DCS, and PCS base-station applications. Features ♦ +23.5dBm Input IIP3 ♦ 1700MHz to 2200MHz RF Frequency Range ♦ 40MHz to 350MHz IF Frequency Range ♦ 1400MHz to

1400MHz to 2000MHz LO Frequency

文件：251.53 Kbytes Page：7 Pages

高线性度、1700MHz至2200MHz下变频混频器，带有LO缓冲器/开关

High-Linearity 1700MHz to 2200MHz Down- Conversion Mixer with LO Buffer/Switch

General Description The MAX9993 high-linearity down-conversion mixer provides 8.5dB of gain, +23.5dBm IIP3, and 9.5dB NF for UMTS, DCS, and PCS base-station applications. Features ♦ +23.5dBm Input IIP3 ♦ 1700MHz to 2200MHz RF Frequency Range ♦ 40MHz to 350MHz IF Frequency Range ♦ 1400MHz to

封装/外壳：20-WQFN 裸露焊盘 包装：带 描述：IC MIXER 1.7-2.2GHZ DWN 20TQFN RF/IF，射频/中频和 RFID 射频混频器

封装/外壳：20-WQFN 裸露焊盘 包装：卷带（TR）带 描述：IC MIXER 1.7-2.2GHZ DWN 20TQFN RF/IF，射频/中频和 RFID 射频混频器

1400MHz to 2000MHz LO Frequency

文件：251.53 Kbytes Page：7 Pages

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg

INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS)PLL CLOCK DRIVER

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs reg