Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers

General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output l

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 功能：解串器 包装：托盘 描述：IC DESERIALIZER 21BIT 48TSSOP 集成电路（IC） 串行器，解串器

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 功能：解串器 包装：卷带（TR） 描述：IC DESERIALIZER 21BIT 48TSSOP 集成电路（IC） 串行器，解串器

12-Bit, 20/40/65 MSPS Dual A/D Converter

GENERAL DESCRIPTION The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output e

System Reset

Outline This IC is a reset IC with a delay circuit which realizes high-precision detection accuracy and is provided in an ultra-small package. Features 1. Internal delay circuit Delay time can be set with an external capacitor. 2. High-precision detection accuracy Vs±1.

12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter

文件：1.72632 Mbytes Page：48 Pages

VRM 8.5 PWM AND TRIPLE LINEAR POWER SYSTEM CONTROLLER

文件：434.77 Kbytes Page：24 Pages