Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

可编程、直流平衡、21位解串器

MAX9210/MAX9214/MAX9220/MAX9222将三路LVDS串行数据输入解串为21位单端LVCMOS/LVTTL输出。随LVDS数据流接收到的并行LVDS时钟，为解串提供时序。输出具有独立的电源，允许1.8V至5V的输出逻辑电平。\n MAX9210/MAX9214/MAX9220/MAX9222具有可编程直流平衡的特点，允许利用交流耦合将串行器和解串器隔离开。解串器解码MAX9209/MAX9213等串行器所发送的数据。\n MAX9210/MAX9214具有上升沿输出锁存，当直流平衡未编程时，这些解串器兼容于非直流平衡21位解串器，如DS90CR216A和DS90CR218 \n• 可编程的直流平衡或非直流平衡 \n• 直流平衡允许交流耦合，以实现更宽的输入共模电压范围 \n• 工作频率可低至8MHz (MAX9210/MAX9220) \n• 下降沿输出锁存(MAX9220/MAX9222) \n• 更慢的输出过渡时间，以减少EMI (MAX9210/MAX9220) \n• 当/PWRDWN为低时，输出处于高阻抗，允许共用总线 \n• 引脚兼容于DS90CR216A/DS90CR218A (MAX9214/MAX9216) \n• 非直流平衡方式支持安全失效输入 \n• 耐压5V的/PWRDWN输入 \n• 无需外围元件的PLL \n• 高达1.785Gbps;

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

Programmable DC-Balance 21-Bit Deserializers

文件：194.64 Kbytes Page：17 Pages

Programmable DC-Balance 21-Bit Deserializers

文件：1.29449 Mbytes Page：17 Pages

QUAD INVERTING TRANSISTOR SWITCH

DESCRIPTION The L9222 monolithic quad transistor switch is designed for high current, high voltage switching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTL-compatible for direct connection to logic c

System Reset

Outline This IC is a reset IC with a delay circuit which realizes high-precision detection accuracy and is provided in an ultra-small package. Features 1. Internal delay circuit Delay time can be set with an external capacitor. 2. High-precision detection accuracy Vs±1.

Dual-Band TDMA LNA/Downconverter IC

Product Description The TQ9222 is a 3-V, RF receiver IC designed specifically for dual-band TDMA applications. Its RF performance meets the requirements of products designed to the IS-136 and GSM standards. The TQ9222 is pin compatible with TQ5121 (cellular band LNA/Mixer) which enables handset d