Low-Cost, High-Speed, Single-Supply, Gain of 2 Buffers with Rail-to-Rail Outputs in SOT23

General Description The MAX4014/MAX4017/MAX4019/MAX4022 are precision, closed-loop, gain of +2 (or -1) buffers featuring high slew rates, high output current drive, and low differential gain and phase errors. These single-supply devices operate from +3.15V to +11V, or from ±1.575V to ±5.5V dual

低成本、高速、单电源、增益为+2的缓冲器，满摆幅输出，SOT23封装

MAX4014/MAX4017/MAX4019/MAX4022是增益为+2（或-1）的精密、闭环缓冲器，具有高压摆率、高输出驱动电流以及低差分增益和相位误差。这些单电源器件采用+3.15V至+11V或±1.575V至±5.5V双电源供电。输入电压范围扩展至负供电轨以上100mV，输出摆幅为轨到轨。\n\n 这些器件仅需要5.5mA的静态电源电流，同时实现200MHz的-3dB带宽和600V/µs的压摆率。此外，MAX4019具有禁用功能，可将电源电流降至400µA。这些器件的输入电压噪声仅为10nV/√Hz，输入电流噪声仅为1.3pA/√Hz。该缓冲器系列非常适合需要宽带宽的低功耗/ • 用于+2或-1闭环增益的内部精密电阻\n\n• 高速：\n• -3dB带宽为200MHz\n\n• 0.1dB增益平坦度：30MHz（最小值6MHz）\n\n• 压摆率：600V/µs\n\n\n\n\n• 3.3V/5.0V单电源供电\n\n• 轨到轨输出摆幅\n\n• 输入电压范围扩展至VEE以上\n\n• 低差分增益/相位：0.04%/0.02°\n\n• 低失真（5MHz时）：\n• -78dBc无杂散动态范围\n\n• 总谐波失真：-75dB\n\n\n\n\n• 高输出驱动电流：±120mA\n\n• 5.5mA低电源电流\n\n• 关断电源电流：400µA\n\n• ;

Low-Cost, High-Speed, Single-Supply, Gain of 2 Buffers with Rail-to-Rail Outputs in SOT23

General Description The MAX4014/MAX4017/MAX4019/MAX4022 are precision, closed-loop, gain of +2 (or -1) buffers featuring high slew rates, high output current drive, and low differential gain and phase errors. These single-supply devices operate from +3.15V to +11V, or from ±1.575V to ±5.5V dual

Low-Cost, High-Speed, Single-Supply, Gain of 2 Buffers with Rail-to-Rail Outputs in SOT23

General Description The MAX4014/MAX4017/MAX4019/MAX4022 are precision, closed-loop, gain of +2 (or -1) buffers featuring high slew rates, high output current drive, and low differential gain and phase errors. These single-supply devices operate from +3.15V to +11V, or from ±1.575V to ±5.5V dual

5-stage Johnson counter

DESCRIPTION The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages