OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The M54/74HC564 and M54HC574 are high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 62 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ HIGH NOISE IMMUNITY VN

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 功能：标准 包装：卷带（TR） 描述：IC FLIP FLOP OCTAL D 3ST 20TSSOP 集成电路（IC） 触发器

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive edge-triggere

Octal 3?뭆tate Noninverting D Flip?묯lop

Octal 3−State Noninverting D Flip−Flop High−Performance Silicon−Gate CMOS The 74HC574 is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. Data meeting the set−up time is clocked to the

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirement

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirement

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive edge-triggere