HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV.

DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGMENT DECODER WITH LATCHED INPUTS fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN

4 TO 16 LINE DECODER/LATCH

文件：289.05 Kbytes Page：12 Pages

HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV.

HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH (INV.)

DESCRIPTION The 74HC4514 and the 74HC4515 are high speed CMOS 4-LINE TO 16-LINE DECODERS WITH LATCHED INPUTS fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. . HIGH SPEED tPD = 18 ns (TYP.) AT VCC = 5 V

HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV.

DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGMENT DECODER WITH LATCHED INPUTS fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN

HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH INV.

DESCRIPTION The M74HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGMENT DECODER WITH LATCHED INPUTS fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN

HC4514: 4 TO 16 LINE DECODER/LATCH HC4515: 4 TO 16 LINE DECODER LATCH (INV.)

DESCRIPTION The 74HC4514 and the 74HC4515 are high speed CMOS 4-LINE TO 16-LINE DECODERS WITH LATCHED INPUTS fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. . HIGH SPEED tPD = 18 ns (TYP.) AT VCC = 5 V

4 TO 16 LINE DECODER/LATCH

文件：289.05 Kbytes Page：12 Pages

4 TO 16 LINE DECODER/LATCH

文件：289.05 Kbytes Page：12 Pages

4 TO 16 LINE DECODER/LATCH

文件：289.05 Kbytes Page：12 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X4:16 24SOP 集成电路（IC） 信号开关，多路复用器，解码器

4 TO 16 LINE DECODER/LATCH

文件：289.05 Kbytes Page：12 Pages

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de