WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER

DESCRIPTION The M54/74HC356 is a high speed CMOS8-CHANNEL MULTIPLEXER/REGISTER (3-State) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 25 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER

DESCRIPTION The M54/74HC356 is a high speed CMOS8-CHANNEL MULTIPLEXER/REGISTER (3-State) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 25 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER

DESCRIPTION The M54/74HC356 is a high speed CMOS8-CHANNEL MULTIPLEXER/REGISTER (3-State) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 25 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

WITH LATCHES 3-STATE 8 CHANNEL MULTIPLEXER/REGISTER

DESCRIPTION The M54/74HC356 is a high speed CMOS8-CHANNEL MULTIPLEXER/REGISTER (3-State) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 25 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

8-input multiplexer/register; 3-state

GENERAL DESCRIPTION The 74HC/HCT356 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-transparent data latches • Transparent address latch • Easily expanding • Compleme

8-to-1-line Data Selector/Multiplexer/Register (with 3-state outputs)

Description This data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data select address is stored in transparent latches that are enabled by a low level address on pin 11, Select Control. Data on the 8 input lines is stored in a parallel inpu

8-to-1-line Data Selectors/Multiplexer/Register(with 3-state outputs)

Description This data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data select address is stored in transparent latches that are enabled by a low level address on pin 11, Select Control. Data on the 8 input lines is stored in a parallel inpu

8-INPUT MULTIPLEXER / RESISTER 3-STATE

文件：337.07 Kbytes Page：8 Pages

HIGH-SPEED CMOS LOGIC(8-INPUT MULTIPLEXER/REGISTER, 3-STATE)

文件：304.38 Kbytes Page：11 Pages