8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE

DESCRIPTION The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated in silicon C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift regist

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

Rad-hard high speed 2 to 6 V CMOS logic series

文件：306.74 Kbytes Page：29 Pages

抗辐照8位3态移位寄存器输出锁存器

8 BIT SHIFT REGISTER WITH OUTPUT LATCHES 3 STATE

DESCRIPTION The M54/74HC595 is a high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated in silicon C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device contains an 8-bit serial-in, parallel-out shift regist

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

Rad-hard high speed 2 to 6 V CMOS logic series

文件：306.74 Kbytes Page：29 Pages

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

Rad-hard high speed 2 to 6 V CMOS logic series

文件：306.74 Kbytes Page：29 Pages

RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)

文件：738.06 Kbytes Page：15 Pages

High Speed CMOS Logic

8-bit shif t registers with 3-state output latches in bare die form Description The 54HC595 is an 8–bit serial-in to parallel-out shift register which drives an 8–bit D–type latch with 3–state outputs. Both register and latch have independent positive triggered clock inputs. All registers c

8-bit shif t registers with 3-state output latches in bare die form

Description The 74HC595 is an 8–bit serial-in to parallel-out shift register which drives an 8–bit D–type latch with 3–state outputs. Both register and latch have independent positive triggered clock inputs. All registers capture data on rising edge and change output on the falling edge. If

8-bit shif t registers with 3-state output latches in bare die form

文件：1.92361 Mbytes Page：9 Pages