OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HC563 INVERTING - HC573 NON INVERTING

DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. ■ HIGH SPEED tPD = 13 ns (T

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features • Common Latch-Enable Control • Common Three-State Output Enable Control • Buffered Inputs • Three-State Outputs • Bus Line Driving Capacity • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) • Fanout (Over Temperature Range) - Standard Outputs

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：286.35 Kbytes Page：14 Pages

High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

文件：288.18 Kbytes Page：14 Pages

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：109.07 Kbytes Page：7 Pages