128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

High Speed Asynchronous SRAM

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description\nThe LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structure ■ Single +3.3V power supply\n■ Access times: 12/15 ns (max.)\n■ Current: Operating: 170mA (max.)\n              Standby: 10mA (max.)\n■ Full static operation, no clock or refreshing required\n■ All inputs and outputs are directly TTL compatible\n■ Common I/O using three-state output\n■ Output enable;

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus struc

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

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125K X 8 BIT HIGH SPEED CMOS SRAM

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128K X 8 BIT HIGH SPEED CMOS SRAM

文件：216.58 Kbytes Page：14 Pages

128K X 8 BIT HIGH SPEED CMOS SRAM

文件：216.58 Kbytes Page：14 Pages

128K X 8 BIT HIGH SPEED CMOS SRAM

文件：216.58 Kbytes Page：14 Pages