丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

丝印代码：LMK04101；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

具有集成式 1430MHz 至 1570MHz VCO 的抖动消除器：3 路输出用于 2VPEC/LVPEC+4 路输出用于 LVCMOS

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

封装/外壳：48-WFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLOCK COND W/PLL 48WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

文件：588.24 Kbytes Page：46 Pages

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

封装/外壳：48-WFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLOCK COND W/PLL 48WQFN 集成电路（IC） 时钟发生器，PLL，频率合成器

Family Clock Jitter Cleaner

文件：1.20015 Mbytes Page：52 Pages

Breake Away Header .025(0.64mm) Square Posts

[FOXCONN] Breake Away Header .025 (0.64mm) Square Posts

Breake Away Header .025(0.64mm) Square Posts

[FOXCONN] Breake Away Header .025 (0.64mm) Square Posts

40.96MHz SAW Filter 9MHz Bandwidth

文件：133.26 Kbytes Page：3 Pages

Coarse Wavelength Division Multiplexer (CWDM) Add/Drop Filter

文件：162.11 Kbytes Page：3 Pages

Coarse Wavelength Division Multiplexer/Demultiplexer (CWDM) Filter

文件：160.11 Kbytes Page：3 Pages