In-Circuit Emulator for Renesas H8/300 and H8/500

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AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trilli

AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trillio

AM69x Processors, Silicon Revision 1.0

1 Features Processor cores: • Up to eight 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2GHz – 2MB shared L2 cache per quad-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Up to Four Deep Learning Accelerators: – Each with up to 8 Trillio

2-Wire Interfaced, 3V to 5.5V, 4-Digit, 9-Segment LED Display Drivers with Keyscan

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