Dual D-type flip-flop with set and reset; positive-edge trigger

文件：305.52 Kbytes Page：6 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

文件：305.52 Kbytes Page：6 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger

文件：305.52 Kbytes Page：6 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Ty

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock trans

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

文件：444.43 Kbytes Page：16 Pages