Consumer Memory

SDRAM Product Guide Memory Division November 2007

256Mb J-die SDRAM Specification

General Description The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronou

SDRAM Product Guide

文件：153.79 Kbytes Page：8 Pages

256Mb J-die SDRAM Specification

General Description The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronou

256Mb J-die SDRAM Specification

General Description The K4S560432J / K4S560832J / K4S561632J is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronou

256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S560832A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are po

256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S560832B is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are po

256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S560832C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are pos

256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S560832D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are pos

SDRAM Product Guide

文件：153.79 Kbytes Page：8 Pages