型号 功能描述 生产厂家&企业 LOGO 操作
K4H510838D

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung
K4H510838D

DDRSDRAMProductGuide

ConsumerMemory

SamsungSamsung Group

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Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

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Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

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Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung

128MbDDRSDRAM

Features •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe(DQS) •Fourbanksoperation •Differentialclockinputs(CKandCK) •DLLalignsDQandDQStransitionwithCKtransition •MRScyclewithaddresskeyprograms -.Readlatency2,2.5(

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

三星三星半导体

Samsung

512MbD-dieDDRSDRAMSpecification66TSOP-IIwithPb-Free(RoHScompliant)

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Dif

SamsungSamsung Group

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Samsung

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

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Samsung

512MbB-dieDDRSDRAMSpecification

KeyFeatures •VDD:2.5V±0.2V,VDDQ:2.5V±0.2VforDDR266,333 •VDD:2.6V±0.1V,VDDQ:2.6V±0.1VforDDR400 •Double-data-ratearchitecture;twodatatransfersperclockcycle •Bidirectionaldatastrobe[DQS](x4,x8)&[L(U)DQS](x16) •Fourbanksoperation •Differentialcl

SamsungSamsung Group

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Samsung

512MbB-dieDDRSDRAMSpecification

文件:392.89 Kbytes Page:24 Pages

SamsungSamsung Group

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Samsung

512MbB-dieDDRSDRAMSpecification54sTSOP-II(400milx441mil)

文件:353.57 Kbytes Page:24 Pages

SamsungSamsung Group

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Samsung

512MbB-dieDDRSDRAMSpecification54sTSOP-II(400milx441mil)

文件:353.57 Kbytes Page:24 Pages

SamsungSamsung Group

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Samsung

K4H510838D产品属性

  • 类型

    描述

  • 型号

    K4H510838D

  • 制造商

    SAMSUNG

  • 制造商全称

    Samsung semiconductor

  • 功能描述

    DDR SDRAM Product Guide

更新时间:2024-5-16 13:06:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
SAMSUNG/三星
07+
NA
880000
明嘉莱只做原装正品现货
SAMSUNG
2023+
BGA
700000
柒号芯城跟原厂的距离只有0.07公分
SAMSUNG
21+
BGA
50000
全新原装正品现货,支持订货
SAMSUNG
23+
TSOP66
30000
代理全新原装现货,价格优势
SAMSUNG/三星
22+
TSSOP66
6000
进口原装 假一罚十 现货
SAMSUNG
2016+
TSOP
5000
全新原装现货,只售原装,假一赔十!
SAMSUNG/三星
19+
BGA
12681
进口原装现货
SAMSUNG
0616-
15
公司优势库存 热卖中!
23+
N/A
36000
正品授权货源可靠
SAMSUNG/三星
23+
NA/
3283
原装现货,当天可交货,原型号开票

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