位置：首页 > IC中文资料第6974页 > K4H510838D
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
K4H510838D | 512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 |   | |
K4H510838D | DDR SDRAM Product Guide Consumer Memory | Samsung 三星 | | |
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 文件：392.89 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 文件：392.89 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 441mil) 文件：353.57 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 441mil) 文件：353.57 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 54 sTSOP-II (400mil x 441mil) 文件：353.57 Kbytes Page：24 Pages | Samsung 三星 | |
K4H510838D产品属性
- 类型
描述
- 型号
K4H510838D
- 制造商
SAMSUNG
- 制造商全称
Samsung semiconductor
- 功能描述
DDR SDRAM Product Guide
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
25+ |
BGA |
996880 |
只做原装,欢迎来电资询 |
|||
SAMSUNG/三星 |
25+ |
BGA |
13800 |
原装,请咨询 |
|||
SAMSUNG/三星 |
2025+ |
TSOP |
5000 |
原装进口价格优 请找坤融电子! |
|||
SAMSUNG/三星 |
24+ |
TSOP |
9600 |
原装现货,优势供应,支持实单! |
|||
SAMSUNG |
24+ |
TSOP66 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
SAMSUNG/三星 |
23+ |
TSOP66 |
5000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
SAMSUNG/三星 |
2023+ |
BGA |
8635 |
全新原装正品,优势价格 |
|||
SAMSUNG |
23+ |
BGA |
12800 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
|||
SAMSUNG/三星 |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
|||
SAMSUNG/三星 |
2447 |
BGA |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
K4H510838D芯片相关品牌
K4H510838D规格书下载地址
K4H510838D参数引脚图相关
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DdatasheetPDF页码索引
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