位置：首页 > IC中文资料第5842页 > K4H1G0438A
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
K4H1G0438A | 1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 |   | |
K4H1G0438A | 1Gb A-die SDRAM Specification | Samsung 三星 | | |
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb A-die SDRAM Specification 文件：366.7 Kbytes Page：24 Pages | Samsung 三星 | | ||
1Gb M-die DDR SDRAM Specification 文件：206.41 Kbytes Page：23 Pages | Samsung 三星 | | ||
1Gb M-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) 文件：206.61 Kbytes Page：23 Pages | Samsung 三星 | |
K4H1G0438A产品属性
- 类型
描述
- 型号
K4H1G0438A
- 制造商
SAMSUNG
- 制造商全称
Samsung semiconductor
- 功能描述
1Gb A-die SDRAM Specification
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SAMSUNG |
6000 |
面议 |
19 |
DIP/SMD |
|||
SAMSUNG/三星 |
22+ |
TSOP |
12032 |
现货,原厂原装假一罚十! |
|||
SAMSUNG/三星 |
23+ |
TSOP |
5000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
SAMSUNG |
23+ |
TSOP |
8560 |
受权代理!全新原装现货特价热卖! |
|||
SAMSUNG/三星 |
20+ |
TSSOP |
35830 |
原装优势主营型号-可开原型号增税票 |
|||
SAMSUNG |
23+ |
TSOP |
12800 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
|||
SAMSUNG/三星 |
2447 |
TSOP |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
SAMSUNG |
1923+ |
TSOP |
12008 |
原装进口现货库存专业工厂研究所配单供货 |
|||
SAMSUNG |
16+ |
SSOP56 |
4000 |
进口原装现货/价格优势! |
|||
三星 |
TSOP |
960 |
一级代理 原装正品假一罚十价格优势长期供货 |
K4H1G0438A规格书下载地址
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DdatasheetPDF页码索引
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