GENERAL DESCRIPTION

This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM. Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152 words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable, Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively.

MCP FEATURES

• Power supply voltage 2.7V to 3.3V

• High performance:

Flash: 70ns maximum access time

PSRAM: 65ns maximum access time

• Package: 107-ball BGA

• Operating Temperature: -30C to +85C

FLASH FEATURES

• Power Dissipation:

Read Current at 1 Mhz: 4 mA maximum

Read Current at 5 Mhz:18 mA maximum

Sleep Mode: 5 µA maximum

• User Configurable Banks

Flash 1 (64 Mbit)

Bank A1: 8Mbit (8KB x 8 and 64KB x 15)

Bank B1: 24Mbit (64KB x 48)

Bank C1: 24Mbit (64KB x 48)

Bank D1: 8Mbit (8KB x 8 and 64KB x 15)

Flash 2 (64 Mbit)

Bank A2: 8Mbit (8KB x 8 and 64KB x 15)

Bank B2: 24Mbit (64KB x 48)

Bank C2: 24Mbit (64KB x 48)

Bank D2: 8Mbit (8KB x 8 and 64KB x 15)

User chooses two virtual banks from a

combination of four physical banks

• Simultaneous R/W Operations (dual virtual bank):

Zero latency between read and write operations; Data

can be programmed or erased in one bank while data

is simultaneously being read from the other bank

• Low-Power Mode:

A period of no activity causes flash to enter a

low-power state

• Erase Suspend/Resume:

Suspends of erase activity to allow a read in the

same bank

• Sector Erase Architecture:

16 sectors of 4K words each and 126 sectors of 32K words

each in Word mode. Any combination of sectors, or

the entire flash can be simultaneously erased

• Erase Algorithms:

Automatically preprograms/erases the flash memory

entirely, or by sector

• Program Algorithms:

Automatically writes and verifies data at specified

address

• Hidden ROM Region:

256 byte with a Factory-serialized secure electronic

serial number (ESN), which is accessible through a

command sequence

• Data Polling and Toggle Bit:

Detects the completion of the program or erase cycle

• Ready-Busy Outputs (RY/BY)

Detection of program or erase cycle completion for

each flash chip

• Over 100,000 write/erase cycles

• Low supply voltage (Vccf ≤ 2.5V) inhibits writes

• WP/ACC input pin:

If VIL, allows partial protection of boot sectors

If VIH, allows removal of boot sector protection

If Vacc, program time is improved

PSRAM FEATURES (32 Mb density)

• Power Dissipation:

Operating: 25 mA maximum

Standby: 110 µA maximum

• Chip Selects: CE1r, CE2r

• Power down feature using CE2r

Sleep Mode: 10 µA maximum

Nap: 65 µA maximum

8 mbit Partial: 80 µA maximum

• Data retention supply voltage: 2.1 V to 3.3V

• Byte data control: LB (DQ0–DQ7), UB (DQ8–DQ15)