FEATURES

• MCP Features

- 128/256Mb OctalRAM (PSRAM)

- 256/512Mb xSPI Flash

- Temp Grades:

Extended: -40°C to +105°C

Auto Grade (A2): -40°C to +105°C

Auto Grade (A3): -40°C to +125°C (1, 2)

- Package:

6mm x 8mm 24-ball 5x5 array TFBGA

• xSPI Flash Features

- 256/512Mb xSPI Flash

- JEDEC standard xSPI interface

- Supports Standard SPI(1-1-1), Multi- I/O

SPI(1-8-8/1-1-8), Octal (8-8-8) Interface

- Low Signal Counts :11 Signal pins (S#, C,

DQS, DQ0~DQ7)+ optional W#, ERR#

- Double Transfer Rate (DTR) Operation

200MHz (400MB/s) at 1.8V VCC

133MHz (266MB/s) at 3.0V VCC

- In-Band, Software & Hardware Reset

- Optional 4-Bank Architecture for READ

while PROGRAM/ERASE operation (3)

- Address Parity Check function supported

- Program Array Data CRC function

supported.

- Data Learning Pattern for training

operation

- Optional Dedicated W#

- Chip Erase with Uniform: Sector/Block

Erase (4/32/128 Kbyte)

- More than 100,000 erase/program cycles

- More than 20-year data retention

• OctalRAM Features

- 128/256Mb OctalRAM with hidden Refresh

- Octal Peripheral Interface (OPI) Protocol

- Low Signal Counts :11 Signal pins (CS#,

SCLK, DQSM, SIO0~SIO7)

- Double Transfer Rate (DTR) Operation

200MHz (400MB/s) at 1.8V VCC (2)

133MHz (266MB/s) at 3.0V VCC (2)

- Source Synchronous Output signal during

Read Operation (DQSM)

- Data Mask during Write Operation (DQSM)

- Configurable Latency for Read/Write

Operation)

- Supports Variable Latency mode and Fixed

Latency mode

- Configurable Wrapped Burst Length :

16, 32, 64, and 128

- Word Order Burst Sequence

- Continuous Burst Operation:

- Continues Read operation until the end of

array address

- Continues Write operation even after the

end of array address