位置:IS61NVVP25672-250B > IS61NVVP25672-250B详情

IS61NVVP25672-250B中文资料

厂家型号

IS61NVVP25672-250B

文件大小

160.93Kbytes

页面数量

29

功能描述

256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

数据手册

下载地址一下载地址二

生产厂商

ISSI

IS61NVVP25672-250B数据手册规格书PDF详情

DESCRIPTION

The 16 Meg NVVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSIs advanced CMOS technology.

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address, data and control

• Interleaved or linear burst sequence control using MODE input

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages

• Single +1.8V (± 5) power supply

• JTAG Boundary Scan

• Industrial temperature available

更新时间:2025-11-1 14:04:00
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