FEATURES

 533MHz DDR operation (1.067 Gb/s/pin data rate)

 38.4Gb/s peak bandwidth (x18 at 533 MHz clock

frequency)

 Reduced cycle time (15ns at 533MHz)

 32ms refresh (8K refresh for each bank; 64K

refresh command must be issued in total,

each 32ms)

 8 internal banks

 Non-multiplexed addresses (address

multiplexing option available)

 SRAM-type interface

 Programmable READ latency (RL), row cycle

time, and burst sequence length

 Balanced READ and WRITE latencies in order

to optimize data bus utilization

 Data mask signals (DM) to mask signal of

WRITE data; DM is sampled on both edges of

DK.

 Differential input clocks (CK, CK#)

 Differential input data clocks (DKx, DKx#)

 On-die DLL generates CK edge-aligned data

and output data clock signals

 Data valid signal (QVLD)

 HSTL I/O (1.5V or 1.8V nominal)

 25-60Ω matched impedance outputs

 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O

 On-die termination (ODT) RTT

 IEEE 1149.1 compliant JTAG boundary scan

 Operating temperature:

Commercial

(TC = 0° to +95°C)

Industrial

(TC = -40°C to +95°C; TA = -40°C to +85°C)