FEATURES

• Low-voltage Core and I/O Power Supplies

VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,

VDD1 = 1.70-1.95V

• High Speed Un-terminated Logic(HSUL_12) I/O

Interface

• Clock Frequency Range : 10MHz to 533MHz

(data rate range : 20Mbps to 1066Mbps per I/O)

• Four-bit Pre-fetch DDR Architecture

• Multiplexed, double data rate, command/address inputs

• Eight internal banks for concurrent operation

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable Read/Write latencies(RL/WL)

and burst lengths(4,8 or 16)

• ZQ Calibration

• On-chip temperature sensor to control self refresh rate

• Partial –array self refresh(PASR)

• Deep power-down mode(DPD)

• Operation Temperature

Commercial (TC = 0°C to 85°C)

Industrial (TC = -40°C to 85°C)

Automotive, A1 (TC = -40°C to 85°C)

Automotive, A2 (TC = -40°C to 105°C)

Automotive, A25 (TC = -40°C to 115°C)(3)

OPTIONS

• Configuration:

− 128Mx16 (16M x 16 x 8 banks)

− 64Mx32 (8M x 32 x 8 banks)

Package:

− 134-ball BGA for x16 / x32

DESCRIPTION

The IS43/46LD16128B/32640B is 2Gbit CMOS

LPDDR2 DRAM. The device is organized as 8 banks

of 16Meg words of 16bits or 8Meg words of 32bits.

This product uses a double-data-rate architecture to

achieve high-speed operation. The double data rate

architecture is essentially a 4N prefetch architecture

with an interface designed to transfer two data words

per clock cycle at the I/O pins. This product offers fully

synchronous operations referenced to both rising and

falling edges of the clock. The data paths are internally

pipelined and 4n bits prefetched to achieve very high

bandwidth.