FEATURES

• Low-voltage Core and I/O Power Supplies

VDD1 = 1.70-1.95V

VDD2 = 1.06-1.17V

VDDQ = 1.06-1.17V (LPDDR4)

VDDQ = 0.57-0.65V (LPDDR4X)

•LVSTL(Low Voltage Swing Terminated Logic) I/O

Interface

• Max. Clock Frequency : 1.6GHz (3.2Gbps)

• 16n Pre-fetch DDR architecture

• Single data rate (multiple cycles) command/

address bus

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable burst lengths (16 or 32)

• ZQ Calibration

• Operation

• Clock-Stop capability

Temperature

Industrial (TC = -40°C to 95°C)

Automotive, A1 (TC = -40°C to 95°C)

Automotive, A2 (TC = -40°C to 105°C)

Automotive, A3 (TC = -40°C to 125°C)

•Configuration:

- 128Mb x16 x 1 channel

- 8 internal banks

• Dynamic ODT :

DQ ODT :VSSQ Termination

CA ODT :VSS Termination

•Internal VREF and VREF Training

• On-Chip ECC:

- Single-bit error correction (per 64-bits)

• Green Package

200-ball BGA (10mm x 14.5mm)

100-ball BGA (10mm x 7.5mm)