FEATURES

• Flexible & Efficient Memory

Architecture

- Memory Cell: 1bit/Memory Cell

- Organization: 512Mb x8, 256Mb x16

- Page Size for x8: (4K + 256) Bytes

- Page Size for x16: (2K + 128) words

- Block Size for x8: 64x (4K + 256) Bytes

- Block Size for x16: 64x (2K + 128) words

- Number of Plane = 1

- Number of Block per Die (LUN) = 2048

• ONFI 1.0 compliant

• Highest performance

- Read Performance:

- Random Read: 25us (Max.)

- Serial Access: 25ns (Max.)

- Write Performance:

- Program time: 300us (typ.), 700us (max.)

- Block Erase time: 3.5ms (typ.), 10ms (max.)

• Voltage and Temp. Ranges

- Single 1.8V (1.7V to 1.95V) Voltage

Supply

- Temp Grades:

- Industrial: -40°C to +85°C

• Reliable CMOS Floating Gate

Technology

- ECC Requirement: 8bit/512Byte

- Endurance: 60K Program/Erase cycles

- Data Retention: 10 years

• Efficient Read and Program modes

- Command/Address/Data Multiplexed I/O

Interface

- Command Register Operation

- Automatic Page 0 Read at Power-Up Option

- Boot from NAND support

- Automatic Memory Download

- NOP: 4 cycles

- Cache Program Operation for High

Performance Program

- Cache Read Operation

- Copy-Back Operation

- OTP operation

- EDO mode

- Block Protection

- Page copy

• Advanced Security Protection

- Hardware Data Protection:

Program/Erase Lockout during Power Transitions

• Industry Standard Pin-out & Packages

- T =48-pin TSOP (Type I)

- B =63-ball VFBGA

GENERAL DESCRIPTION

The device has 4352-byte static registers which allow program and read data to be transferred between the register

and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit

(256Kbytes + 16Kbytes).

Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for

address and command inputs as well as data input/output.

The copy back function allows the optimization of defective blocks management: when a page program

operation fails, the data can be directly programmed in another page inside the same array section

without the time consuming serial data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is

copied into the Flash array.

This pipelined program operation improves the program throughput when long files are written inside

the memory. A cache read feature is also implemented. This feature allows to dramatically improving

the read throughput when consecutive pages have to be streamed out. This device includes extra

feature: Automatic Read at Power Up.