Description

The Intersil ACS521MS is a Radiation Hardened 8 bit magnitude comparator device. It provides a low output YB when Word A equals word B and input GB is low. All other input states cause a high output.

The ACS521MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The ACS521MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).

Features

• Devices QML Qualified in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96709 and Intersil’ QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

    - VIL = 30 of VCC Max

    - VIH = 70 of VCC Min

• Input Current ≤ 1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)