INTRODUCTION

Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.

■ 80C186 Upgrade for Power Critical Applications

■ Fully Static Operation

■ True CMOS Inputs and Outputs

■ Integrated Feature Set

— Static 186 CPU Core

— Power Save, Idle and Powerdown Modes

— Clock Generator

— 2 Independent DMA Channels

— 3 Programmable 16-Bit Timers

— Dynamic RAM Refresh Control Unit

— Programmable Memory and Peripheral Chip Select Logic

— Programmable Wait State Generator

— Local Bus Controller

— System-Level Testing Support (High Impedance Test Mode)

■ Speed Versions Available (5V):

— 25 MHz (80C186EA25/80C188EA25)

— 20 MHz (80C186EA20/80C188EA20)

— 13 MHz (80C186EA13/80C188EA13)

■ Speed Versions Available (3V):

— 13 MHz (80L186EA13/80L188EA13)

— 8 MHz (80L186EA8/80L188EA8)

■ Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O

■ Supports 80C187 Numeric Coprocessor Interface (80C186EA only)

■ Available in the Following Packages:

— 68-Pin Plastic Leaded Chip Carrier (PLCC)

— 80-Pin EIAJ Quad Flat Pack (QFP)

— 80-Pin Shrink Quad Flat Pack (SQFP)

■ Available in Extended Temperature Range (b40§C to a85§C)